This invention relates to the fabrication of very-large-scale-integrated (VLSI) devices and, more particularly, to a technique for achieving high selectivity while dry etching a layer that is masked by a thin resist pattern.
A particularly advantageous VLSI device fabrication process characterized by submicron resolution with excellent linewidth control and step coverage is described in J. M. Moran and D. Maydan in "High Resolution, Steep Profile, Resist Patterns", in The Bell System Technical Journal, Vol. 58, No. 5, May-June 1979, pp. 1027-1036. This technique, which is sometimes referred to as the trilevel process, is also described in a commonly assigned copending U.S. application of D. B. Fraser, D. Maydan and J. M. Moran designated Ser. No. 941,369, filed Sept. 11, 1978, now U.S. Pat. No. 4,244,799. In the trilevel process, a relatively thin layer must be selectively etched using a thin high-resolution resist pattern as the mask therefor. The relatively thin layer comprises, for example, a 0.12-micrometers (.mu.m)-thick film of silicon dioxide (SiO.sub.2).
When the trilevel process is utilized for micron and submicron pattern transfer, the material employed to form the required thin high-resolution resist pattern therein is typically an electron-sensitive resist such as poly(glycidyl methacrylate-co-ethyl acrylate) also known as COP or poly(olefin sulfone) also known as PBS or an X-ray-sensitive resist such as a mixture of poly(2,3-dichloro-1-propyl acrylate) and poly(glycidyl methacrylate-co-ethyl acrylate) also known as DCOPA. As masking materials, these high-resolution resists do not, however, always exhibit a sufficiently high resistance to the dry etching processes typically utilized to etch the underlying SiO.sub.2 layer. Thus, for example, when resist-masked SiO.sub.2 is patterned in a reactive sputter etching step in a CHF.sub.3 plasma, the SiO.sub.2 -to-resist etch ratio (etch selectivity) is in practice sometimes so low that the loss of linewidth that results from resist erosion during pattern transfer is unacceptably high for some VLSI device fabrication purposes.
Accordingly, continuing efforts have been made by workers in the VLSI device fabrication field directed at trying to improve the aforespecified etch selectivity. It was recognized that such efforts, if successful, would make it feasible to utilize extremely thin resist masks in a device fabrication process characterized by high-resolution features with excellent linewidth control.